84025EM

www.icst.com/products/hiperclocks.html

REV. A APRIL 16, 2003

8

Integrated

Circuit

Systems, Inc.

ICS84025

PRELIMINARY

Figure 4A shows a schematic example of using an ICS84025. In

this example, the input is a 25MHz parallel resonant crystal with

load capacitor CL=18pF. The frequency fine tuning capacitors

C1 and C2 is 22pF and 18pF respectively. This example also

shows logic control input handling. The configuration is set at

F_SEL[1:0]=11 therefore the output frequency is 125MHz. It is

recommended to have one decouple capacitor per power pin.

Each decoupling capacitor should be located as close as pos-

sible to the power pin. The low pass filter R7, C11 and C16 for

clean analog supply should also be located as close to the V

DDA

pin as possible.

VDD

RD2

SP

R1

43

F_SEL1

RD4

SP

C7

0.1u

(U1,17)

C3

0.1u

SP = Spare, Not Installed

F_SEL1

RU3

1K

C2

18p

RD3

SP

VDD

C16

10u

VDD

C6

0.1u

VDDA

PLL_SEL

C5

0.1u

X1

25MHz,18pF

R6

43

RU4

1K

(U1,13)

F_SEL0

PLL_SEL

(U1,5)

C1

22p

Zo = 50

(U1,1)

RU2

1K

C11

0.1u

R7

10

F_SEL0

C4

0.1u

(U1,9)

Zo = 50

VDD=3.3V

U1

ICS84025

1

2

3

4

5

6

7

8

9

10

11

15

17

18

19

20

21

22

23

24

14

12

13

16

VDDO

Q0

GND

Q1

VDDO

Q2

GND

Q3

VDDO

Q4

GND

GND

VDD

VDDA

GND

XTAL2

XTAL1

MR

F_SEL1

F_SEL0

NC

Q5

VDDO

PLL_SEL

VDD