MPC866 datasheet(72/96 Pages) NXP

72 / 96 page

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

UTOPIA AC Electrical Specifications

Figure 71 shows the I2C bus timing.

Figure 71. I2C Bus Timing Diagram

13 UTOPIA AC Electrical Specifications

Table 30 through Table 32 show the AC electrical specifications for the UTOPIA interface.

Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications

Num

Signal Characteristic

Direction

Min

Max

Unit

UtpClk rise/fall time (Internal clock option)

Output

—

Duty cycle

Frequency

—

MHz

UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr-active

delay (and PHREQ and PHSEL active delay in MPHY mode)

Output

UTPB, SOC, Rxclav and Txclav setup time

Input

—

UTPB, SOC, Rxclav and Txclav hold time

Input

—

Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications

Num

Signal Characteristic

Direction

Min

Max

Unit

UtpClk rise/fall time (Internal clock option)

Output

—

Duty cycle

Frequency

—

MHz

UTPB, SOC, RxEnb, TxEnb, RxAddr and TxAddr active

delay (PHREQ and PHSEL active delay in MPHY mode)

Output

UTPB_Aux, SOC_Aux, Rxclav, and Txclav setup time

Input

—

UTPB_Aux, SOC_Aux, Rxclav, and Txclav hold time

Input

—

SCL

202

205

203

207

204

208

206

209

211

210

SDA

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