FXLS93421 datasheet(53/254 Pages) NXP

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NXP Semiconductors

FXLS9xxxx

Dual channel inertial sensor

2. Write 0x40 to the WRITE_OTP_EN register to set the MARGIN_RD_EN bit. This

initiates the OTP margin read test which completes the sequence listed in steps a

through i.

a. The UF2 block is read. The ECC is checked for double bit errors and the CRC

is verified. If an ECC error or CRC error exists or if UF2 block is unlocked, the

MARGIN_RD_ERR bit is set and the test is terminated.

b. A margin read low test is run with the read threshold reduced by 25 %. The data

is checked against the expected values in the mirror registers. If a double bit ECC

error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and

the test is terminated.

c. A margin read high test is run with the read threshold increased by 25 %. The data

is checked against the expected values in the mirror registers. If a double bit error

or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test

is terminated.

d. The UF0 block is read. The ECC is checked for double bit errors and the CRC

is verified. If an ECC error or CRC error exists or if UF0 block is unlocked, the

MARGIN_RD_ERR bit is set and the test is terminated.

e. A margin read low test is run with the read threshold reduced by 25 %. The data

is checked against the expected values in the mirror registers. If a double bit ECC

error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and

the test is terminated.

f. A margin read high test is run with the read threshold increased by 25 %. The data

is checked against the expected values in the mirror registers. If a double bit error

or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test

is terminated.

g. The UF1 block is read. The ECC is checked for double bit errors and the CRC

is verified. If an ECC error or CRC error exists or if UF1 block is unlocked, the

MARGIN_RD_ERR bit is set and the test is terminated.

h. A margin read low test is run with the read threshold reduced by 25 %. The data

is checked against the expected values in the mirror registers. If a double bit ECC

error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and

the test is terminated.

i. A margin read high test is run with the read threshold increased by 25 %. The data

is checked against the expected values in the mirror registers. If a double bit error

or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test

is terminated.

3. Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT bit is set and

the MARGIN_RD_ERR bit is cleared.

4. Delay 1.5 ms minimum.

5. Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT bit is cleared.

Check the state of the MARGIN_RD_ERR bit.

• If the MARGIN_RD_ERR bit is cleared, the margin read test passed.

• If the MARGIN_RD_ERR bit is set, the margin read test failed.

6. When the test is complete, the MARGIN_RD_EN bit is cleared.

7. When the test is complete and the MREAD_STAT register has been read, the

MARGIN_RD_ACT and the MARGIN_RD_ERR bit are cleared.

The user enabled OTP margin read test can only be enabled when the ENDINIT bit is not

set.

FXLS9xxxx

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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