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M69KB096AA Datasheet(PDF) 38 Page - STMicroelectronics |
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M69KB096AA Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 48 page ![]() M69KB096AA 38/48 Figure 28. Asynchronous Write Followed by Synchronous Burst Read (4-word) AC Waveforms Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay. 2. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns. 3. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met. |
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