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MPC885ZP80 Datasheet(PDF) 69 Page - NXP Semiconductors |
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MPC885ZP80 Datasheet(HTML) 69 Page - NXP Semiconductors |
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69 / 87 page ![]() MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 69 UTOPIA AC Electrical Specifications 13 UTOPIA AC Electrical Specifications Table 30, Table 31, and Table 32, show the AC electrical specifications for the UTOPIA interface. Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (internal clock option) Output 4 ns Duty cycle 50 50 % Frequency 33 MHz U2 UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (PHREQ and PHSEL active delay in multi-PHY mode) Output 2 16 ns U3 UTPB, SOC, Rxclav, and Txclav setup time Input 4 ns U4 UTPB, SOC, Rxclav, and Txclav hold time Input 1 ns Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (Internal clock option) Output 4 ns Duty cycle 50 50 % Frequency 33 MHz U2 UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (PHREQ and PHSEL active delay in multi-PHY mode) Output 2 16 ns U3 UTPB_Aux, SOC_Aux, Rxclav, and Txclav setup time Input 4 ns U4 UTPB_Aux, SOC_Aux, Rxclav, and Txclav hold time Input 1 ns Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (external clock option) Input 4 ns Duty cycle 40 60 % Frequency 33 MHz U2 UTPB, SOC, Rxclav, and Txclav active delay Output 2 16 ns U3 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup time Input 4 ns U4 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time Input 1 ns |
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