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MPC885ZP80 Datasheet(PDF) 27 Page - NXP Semiconductors

No. de pieza MPC885ZP80
Descripción Electrónicos  MPC885/MPC880 PowerQUICC Hardware Specifications
PDF  87 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC885ZP80 Datasheet(HTML) 27 Page - NXP Semiconductors

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MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Freescale Semiconductor
27
Bus Signal Timing
Figure 12 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in
the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
Figure 12. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 13 through Figure 16 provide the timing for the external bus read controlled by various GPCM
factors.
Figure 13. External Bus Read Timing (GPCM Controlled—ACS = 00)
CLKOUT
TA
D[0:31]
B20
B21
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31]
B11
B12
B23
B8
B22
B26
B19
B18
B25
B28



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