LTC2430IGN datasheet(25/40 Pages) LINER

25 / 40 page

LTC2430/LTC2431

24301f

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/

°C) are

used for the external source impedance seen by IN+ and

IN–, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-

tive values over the entire temperature and voltage range).

Even for the most stringent applications, a one-time

calibration operation may be sufficient.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (

±10nA max), results

in a small offset shift. A 100

Ω source resistance will create

a 0.1

µV typical and 1µV maximum offset voltage.

Reference Current

In a similar fashion, the LTC2430 or LTC2431 samples the

differential reference pins REF+ and REF– transfering small

amount of charge to and from the external driving circuits

thus producing a dynamic reference current. This current

does not change the converter offset, but it may degrade

the gain and INL performance. The effect of this current

can be analyzed in the same two distinct situations.

For relatively small values of the external reference capaci-

tors (CREF < 0.01µF), the voltage on the sampling capacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for CREF will deteriorate the converter offset and

gain performance without significant benefits of reference

filtering and the user is advised to avoid them.

Larger values of reference capacitors (CREF > 0.01µF)

may be required as reference filters in certain configura-

tions. Such capacitors will average the reference sam-

pling charge and the external source resistance will see a

quasi constant reference differential impedance. When

FO = LOW (internal oscillator and 60Hz notch), the typical

differential reference resistance is 15.6M

Ω which will

generate a gain error of approximately 0.032ppm for each

ohm of source resistance driving REF+ or REF–. When FO

= HIGH (internal oscillator and 50Hz notch), the typical

differential reference resistance is 18.7M

Ω which will

generate a gain error of approximately 0.027ppm for each

ohm of source resistance driving REF+ or REF –. When FO

is driven by an external oscillator with a frequency fEOSC

(external conversion clock operation), the typical differ-

ential reference resistance is 2.4 • 1012/fEOSCΩ and each

ohm of source resistance drving REF+ or REF– will result

in 0.206 • 10–6 • fEOSCppm gain error. The effect of the

source resistance on the two reference pins is additive

with respect to this gain error. The typical FS errors for

various combinations of source resistance seen by the

REF+ and REF– pins and external capacitance CREF con-

nected to these pins are shown in Figures 17 and 18.

Typical – FS errors are similar to + FS errors with opposite

polarity.

In addition to this gain error, the converter INL perfor-

mance is degraded by the reference source impedance.

When FO = LOW (internal oscillator and 60Hz notch), every

100

Ω of source resistance driving REF+ or REF– translates

APPLICATIO S I FOR ATIO

Figure 17b. – FS Error vs RSOURCE at REF+ or REF– (Small CIN)

Figure 17a. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)

RSOURCE (Ω)

–50

–40

–30

–20

–10

100

10k

2431 F17a

100k

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 3.75V

VIN– = 1.25V

FO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0pF

CREF = 0.001µF

CREF = 100pF

RSOURCE (Ω)

–10

100

10k

2431 F17b

100k

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 1.25V

VIN– = 3.75V

FO = GND

TA = 25°C

CREF = 0.01µF

CREF = 0pF

CREF = 0.001µF

CREF = 100pF

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