LTC2430IGN datasheet(21/40 Pages) LINER

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LTC2430/LTC2431

24301f

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

then immediately begins outputting data. The data output

cycle begins on the first rising edge of SCK and ends after

the 24th rising edge. Data is shifted out the SDO pin on

each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used

to shift the conversion result into external circuitry. EOC

can be latched on the first rising edge of SCK and the last

bit of the conversion result can be latched on the 24th

rising edge of SCK. After the 24th rising edge, SDO goes

HIGH (EOC = 1) indicating a new conversion is in progress.

SCK remains HIGH during the conversion.

PRESERVING THE CONVERTER ACCURACY

The LTC2430/LTC2431 are designed to reduce as much as

possible the conversion result sensitivity to device

decoupling, PCB layout, antialiasing circuits, line fre-

quency perturbations and so on. Nevertheless, in order to

preserve the extreme accuracy capability of this part,

some simple precautions are desirable.

Digital Signal Levels

The LTC2430/LTC2431’s digital interface is easy to use.

The digital inputs (FO, CS and SCK in External SCK mode

of operation) accept standard TTL/CMOS logic levels and

the internal hysteresis receivers can tolerate edge rates as

slow as 100

µs.However,someconsiderationsarerequired

to take advantage of the exceptional accuracy and low

supply current of this converter.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

While a digital input signal is in the range 0.5V to

(VCC – 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (FO, CS and SCK

in External SCK mode of operation) is within this range,

the LTC2430/LTC2431 power supply current may in-

crease even if the signal in question is at a valid logic level.

For micropower operation, it is recommended to drive all

digital input signals to full CMOS levels [VIL < 0.4V and

VOH > (VCC – 0.4V)].

During the conversion period, the undershoot and/or

overshoot of a fast digital signal connected to the LTC2430/

LTC2431 pins may severely disturb the analog to digital

conversion process. Undershoot and overshoot can oc-

cur because of the impedance mismatch at the converter

pin when the transition time of an external control signal

is less than twice the propagation delay from the driver to

LTC2430/LTC2431. For reference, on a regular FR-4 board,

signal propagation velocity is approximately 183ps/inch

for internal traces and 170ps/inch for surface traces.

Thus, a driver generating a control signal with a minimum

transition time of 1ns must be connected to the converter

pin through a trace shorter than 2.5 inches. This problem

becomes particularly difficult when shared control lines

are used and multiple reflections may occur. The solution

is to carefully terminate all transmission lines close to

their characteristic impedance.

Parallel termination near the LTC2430/LTC2431 pin will

eliminate this problem but will increase the driver power

dissipation. A series resistor between 27

Ω and 56Ω

placed near the driver or near the LTC2431 pin will also

eliminate this problem without additional power dissipa-

tion. The actual resistor value depends upon the trace

impedance and connection topology.

An alternate solution is to reduce the edge rate of the

control signals. It should be noted that using very slow

edges will increase the converter power supply current

during the transition time. The differential input and refer-

ence architecture reduce substantially the converter’s

sensitivity to ground currents.

Particular attention must be given to the connection of the

FO signal when the converter (LTC2430 or LTC2431) is

used with an external conversion clock. This clock is active

during the conversion time and the normal mode rejection

provided by the internal digital filter is not very high at this

frequency. A normal mode signal of this frequency at the

converter reference terminals may result into DC gain and

INL errors. A normal mode signal of this frequency at the

converter input terminals may result into a DC offset error.

Such perturbations may occur due to asymmetric capaci-

tive coupling between the FO signal trace and the converter

input and/or reference connection traces. An immediate

solution is to maintain maximum possible separation

APPLICATIO S I FOR ATIO

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