KSZ8563R datasheet(13/221 Pages) MICROCHIP

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DS00002418D-page 13

KSZ8563R

Port 3

Receive/

Reference

Clock

RX_CLK/

REFCLKO

I/O24

MII Mode: RX_CLK is the Port 3 25/2.5MHz Receive

Clock. In PHY mode this pin is an output, in MAC mode it is

an input.

RMII Mode: REFCLKO is the Port 3 50MHz Reference

Clock output when in RMII Clock mode. This pin is unused

when in RMII Normal mode.

RGMII Mode: RX_CLK is the Port 3 125/25/2.5MHz

Receive Clock output.

Port 3

Receive Data

Valid / Carrier

Sense / Control

RX_DV/

CRS_DV/

RX_CTL

IPD/O24

MII Mode: RX_DV is the Port 3 Received Data Valid output.

RMII Mode: CRS_DV is the Carrier Sense / Receive Data

Valid output.

RGMII Mode: RX_CTL is the Receive Control output.

Note:

This pin also provides configuration strap func-

tions during hardware/software resets. Refer to

Section 3.2.1, "Configuration Straps" for addi-

tional information.

Port 3

Receive Error

RX_ER

IPD/O24

MII Mode: Port 3 Receive Error output.

RMII/RGMII Modes: Not used. Do not connect this pin in

these modes of operation.

Note:

This pin also provides configuration strap func-

tions during hardware/software resets. Refer to

Section 3.2.1, "Configuration Straps" for addi-

tional information.

Port 3

Receive Data 3

RXD3

IPD/O24

MII/RGMII Modes: Port 3 Receive Data bus bit 3.

RMII Mode: Not used. Do not connect this pin in this mode

of operation.

Note:

This pin also provides configuration strap func-

tions during hardware/software resets. Refer to

Section 3.2.1, "Configuration Straps" for addi-

tional information.

Port 3

Receive Data 2

RXD2

IPD/O24

MII/RGMII Modes: Port 3 Receive Data bus bit 2.

RMII Mode: Not used. Do not connect this pin in this mode

of operation.

Note:

This pin also provides configuration strap func-

tions during hardware/software resets. Refer to

Section 3.2.1, "Configuration Straps" for addi-

tional information.

Port 3

Receive Data 1

RXD1

IPD/O24

MII/RMII/RGMII Modes: Port 3 Receive Data bus bit 1.

Note:

This pin also provides configuration strap func-

tions during hardware/software resets. Refer to

Section 3.2.1, "Configuration Straps" for addi-

tional information.

TABLE 3-2:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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