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STM32G474PBY3TR Datasheet(PDF) 120 Page - STMicroelectronics

No. de pieza STM32G474PBY3TR
Descripción Electrónicos  Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer
PDF  236 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G474PBY3TR Datasheet(HTML) 120 Page - STMicroelectronics

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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
120/236
DS12288 Rev 5
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with a 32.768 kHz crystal
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
Table 42. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
1. Guaranteed by design.
Symbol
Parameter
Conditions(2)
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
Min
Typ
Max
Unit
IDD(LSE) LSE current consumption
LSEDRV[1:0] = 00
Low drive capability
-250
-
nA
LSEDRV[1:0] = 01
Medium low drive capability
-315
-
LSEDRV[1:0] = 10
Medium high drive capability
-500
-
LSEDRV[1:0] = 11
High drive capability
-630
-
Gmcritmax
Maximum critical crystal
gm
LSEDRV[1:0] = 00
Low drive capability
--
0.5
µA/V
LSEDRV[1:0] = 01
Medium low drive capability
--
0.75
LSEDRV[1:0] = 10
Medium high drive capability
--
1.7
LSEDRV[1:0] = 11
High drive capability
--
2.7
tSU(LSE)(3)
3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
Startup time
VDD is stabilized
-
2
-
s
MS30253V2
OSC32_IN
OSC32_OUT
Drive
programmable
amplifier
fLSE
32.768 kHz
resonator
Resonator with integrated
capacitors
CL1
CL2



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