STM32G474PBY3TR datasheet(19/236 Pages) STMICROELECTRONICS

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DS12288 Rev 5

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STM32G474xB STM32G474xC STM32G474xE

Functional overview

3.4

Embedded Flash memory

The STM32G474xB/xC/xE devices feature 512 kbytes of embedded Flash memory which is

available for storing programs and data.

The Flash interface features:

–

Single or dual bank operating modes

–

Read-while-write (RWW) in dual bank mode

This feature allows to perform a read operation from one bank while an erase or program

operation is performed to the other bank. The dual bank boot is also supported.

Flexible protections can be configured thanks to the option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels of protection are

available:

– Level 0: no readout protection

– Level 1: memory readout protection; the Flash memory cannot be read from or written

to if either the debug features are connected or the boot in RAM or bootloader are

selected

– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial

wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This

selection is irreversible.

•

Write protection (WRP): the protected area is protected against erasing and

programming.

•

Proprietary code readout protection (PCROP): a part of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only

and it can only be reached by the STM32 CPU as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An

additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not

when the RDP protection is changed from Level 1 to Level 0.

•

Securable memory area: a part of Flash memory can be configured by option bytes to

be securable. After reset this securable memory area is not secured and it behaves like

the remainder of main Flash memory (execute, read, write access). When secured, any

access to this securable memory area generates corresponding read/write error.

Purpose of the Securable memory area is to protect sensitive code and data (secure

keys storage) which can be executed only once at boot, and never again unless a new

reset occurs.

The Flash memory embeds the error correction code (ECC) feature supporting:

•

Single error detection and correction

•

Double error detection

•

The address of the ECC fail can be read in the ECC register

•

1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The

OTP area is available in Bank 1 only. The OTP data cannot be erased and can be

written only once.

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