STM32G474PBY3XXX datasheet(47/236 Pages) STMICROELECTRONICS

47 / 236 page

DS12288 Rev 5

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STM32G474xB STM32G474xC STM32G474xE

Functional overview

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

3.38

Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI

flash memories. It can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the QUADSPI registers

•

Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external Flash is memory mapped and is seen by the

system as if it were an internal memory.

Both throughput and capacity can be increased two-fold using dual-flash mode, where two

quad SPI flash memories are accessed simultaneously.

The Quad SPI interface supports:

•

Indirect mode: all the operations are performed using the QUADSPI registers

•

Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external Flash is memory mapped and is seen by the

system as if it were an internal memory

•

Three functional modes: indirect, status-polling, and memory-mapped

•

SDR and DDR support

•

Fully programmable opcode for both indirect and memory mapped mode

•

Fully programmable frame format for both indirect and memory mapped mode

–

Each of the 5 following phases can be configured independently (enable, length,

single/dual/quad communication)

–

Instruction phase

–

Address phase

–

Alternate bytes phase

–

Dummy cycles phase

–

Data phase

•

Integrated FIFO for reception and transmission

•

8, 16, and 32-bit data accesses are allowed

•

DMA channel for indirect mode operations

•

Programmable masking for external flash flag management

•

Timeout management

•

Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

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