STM32G474PBY3XXX datasheet(46/236 Pages) STMICROELECTRONICS

46 / 236 page

Functional overview

STM32G474xB STM32G474xC STM32G474xE

46/236

DS12288 Rev 5

The digital controller handles notably:

•

USB Type-C level detection with de-bounce, generating interrupts

•

FRS detection, generating an interrupt

•

Byte-level interface for USB Power Delivery payload, generating interrupts (DMA

compatible)

•

USB Power Delivery timing dividers (including a clock pre-scaler)

•

CRC generation/checking

•

4b5b encode/decode

•

Ordered sets (with a programmable ordered set mask at receive)

•

Frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the

capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.36

Clock recovery system (CRS)

The devices embed a special block which allows automatic trimming of the internal 48 MHz

oscillator to guarantee its optimal accuracy over the whole device operational range. This

automatic trimming is based on the external synchronization signal, which could be either

derived from USB SOF signalization, from LSE oscillator, from an external signal on

CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also

possible to combine automatic trimming with manual trimming action.

3.37

Flexible static memory controller (FSMC)

The Flexible static memory controller (FSMC) includes two memory controllers:

•

The NOR/PSRAM memory controller

•

The NAND/memory controller

This memory controller is also named Flexible memory controller (FMC).

The main features of the FMC controller are the following:

•

Interface with static-memory mapped devices including:

–

Static random access memory (SRAM)

–

NOR Flash memory/OneNAND Flash memory

–

PSRAM (4 memory banks)

–

NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

–

Ferroelectric RAM (FRAM)

•

8-,16- bit data bus width

•

Independent Chip Select control for each memory bank

•

Independent configuration for each memory bank

•

Write FIFO

•

The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.

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