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LTC4230

4230f

USING AN EXTERNAL GATE CAPACITOR

The LTC4230 automatically limits the inrush current in one

of two ways: by controlling the GATE

n pin voltage slew rate

or by actively limiting the inrush current. The LTC4230

uses GATE

n voltage slew rate limiting when CLOADn is

small and/or the inrush current limit is set high. If GATE

voltage slew rate control is preferred with large CLOADn, an

external capacitor (CGX)canbeusedfromGATEntoground,

as shown in Figure 7. According to Equation 3, adding CGX

slows the GATE

n voltage slew rate at the expense of slower

system turn-on and turn-off time. Should this technique

be used, values for CGX less than 150nF are recommended.

ELECTRONIC CIRCUIT BREAKER

The LTC4230 features an electronic circuit breaker func-

tion. It disconnects loads from power supplies when

shorts or excessive load current conditions occur on any

of the supplies and generates a FAULT signal. If a circuit

breaker trips, its GATE

n pin is immediately pulled to

ground, the external N-channel MOSFET is quickly turned

OFF and FAULT is latched low.

The circuit breaker trips whenever the voltage across the

sense resistor exceeds two different levels, each level set

by the LTC4230’s SLOW COMP

n and FAST COMPn (see

Block Diagram). The SLOW COMP

n trips the circuit

breaker if the voltage across the SENSE

n resistor

(VCCn – VSENSEn = VCB) is greater than 50mV for 10µs.

There may be applications where this comparator’s re-

sponse time is not long enough, for example, because of

excessive supply voltage noise. To adjust the response

time of the SLOW COMP

n, a capacitor is used at the

LTC4230’s FILTER pin (see section on Adjusting SLOW

COMP

n’s Response Time). The FAST COMPn trips the

circuit breaker to protect against fast load overcurrents if

the transient voltage across the sense resistor is greater

than 150mV for 500ns. The response time of the LTC4230’s

FAST COMP

n is fixed.

The timing diagram of Figure 6 illustrates when the

LTC4230’s electronic circuit breaker is armed. After the

first timing cycle, the LTC4230’s FAST COMP

n is armed

at Time Point 5. Arming FAST COMP

n at Time Point 5

ensures that the system is protected against a short-

circuit condition during the second timing cycle after

CLOADn has been fully charged. At Time Point 8, SLOW

COMP

n is armed when the internal control loop is disen-

gaged.

The timing diagrams in Figures 8 and 9 illustrate the opera-

tion of the LTC4230 when the load current conditions exceed

the thresholds of the FAST COMP

n (VCB(FAST) > 150mV)

and SLOW COMP

n (VCB(SLOW) > 50mV), respectively.

Si4410DY

RSENSE

0.007

Ω

CGX*

CLOAD

4230 F07

VCCn

SENSE

LTC4230**

GATE

36k

VOUT

VIN

15k

VALUES

≤150nF SUGGESTED

ADDITIONAL DETAILS OMITTED

FOR CLARITY

dVGATEn

VGATE SLEW RATE CONTROL

µA

CGATE + CGX

()

Figure 7. Using an External Capacitor at GATE for

GATE Voltage Slew Rate Control and Large CLOAD

An external gate capacitor may also be useful to decrease

or eliminate current spikes through the MOSFET when

power is first applied. At power-up, the instantaneous in-

put voltage step attempts to pull the MOSFET gate up

through the MOSFET’s drain-to-gate capacitance. If the

MOSFET’s CISS is small, the gate can be pulled up high

enough to turn on the MOSFET, thereby allowing a current

spike to the output. This event occurs during the time that

the LTC4230 is coming out of UVLO and getting its intel-

ligence to hold the GATE pin low. An external capacitor

attenuates the voltage to which the GATE is pulled up and

eliminates the current spike. The value required is depen-

dent on the MOSFET capacitance specifications. In typical

applications, this capacitor is not required.

APPLICATIO S I FOR ATIO

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