JS28F256P30T85 datasheet(84/102 Pages) INTEL

No. de pieza	JS28F256P30T85

Descripción Electrónicos	Intel StrataFlash Embedded Memory

PDF	102 Pages

Scroll/Zoom	100%

Fabricante Electrónico	INTEL [Intel Corporation]

Página de inicio	http://www.intel.com

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84 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM

running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes).

BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored.

The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or

Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where

the partition's output mux is presently pointing to.

Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then

move to the Ready State.

WA0 refers to the block address latched during the first write cycle of the current operation.

JS28F256P30T85 Datasheet(PDF) 84 Page - Intel Corporation