JS28F256P30T85 datasheet(75/102 Pages) INTEL

75 / 102 page

1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

14.0

Special Read States

The following sections describe non-array read states. Non-array reads can be performed in

asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous

single-word mode. When non-array reads are performed in asynchronous page mode only the first

data is valid and all subsequent data are undefined. When a non-array read operation occurs as

synchronous burst mode, the same word of data requested will be output on successive clock edges

until the burst length requirements are satisfied.

Refer to the following waveforms for more detailed information:

• Figure 16, “Asynchronous Single-Word Read (ADV# Low)” on page 38

• Figure 17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38

• Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39

14.1

Read Status Register

To read the Status Register, issue the Read Status Register command at any address. Status Register

information is available to which the Read Status Register, Word Program, or Block Erase

command was issued. Status Register data is automatically made available following a Word

Program, Block Erase, or Block Lock command sequence. Reads from the device after any of these

command sequences outputs the device’s status until another valid command is written (e.g. Read

Array command).

The Status Register is read using single asynchronous-mode or synchronous burst mode reads.

Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous

mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status

must be toggled to update status data.

The Device Write Status bit (SR[7]) provides overall status of the device. Status register bits

SR[6:1] present status and error information about the program, erase, suspend, VPP, and block-

locked operations.

Table 28.

Status Register Description (Sheet 1 of 2)

Status Register (SR)

Default Value = 0x80

Device

Write Status

Erase

Suspend

Status

Erase

Status

Program

Status

VPP Status

Program

Suspend

Status

Block-

Locked

Status

BEFP

Status

DWS

ESS

VPPS

PSS

BLS

BWS

654

Bit

Name

Description

Device Write Status

(DWS)

0 = Device is busy; program or erase cycle in progress; SR[0] valid.

1 = Device is ready; SR[6:1] are valid.

Erase Suspend Status

(ESS)

0 = Erase suspend not in effect.

1 = Erase suspend in effect.

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