IS25LP032D-RGLA3:P datasheet(42/118 Pages) ISSI

42 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh)

The FRQO instruction is used to read memory data on four output pins each at up to a 133 MHz clock.

A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad Output instruction.

The FRQO instruction code is followed by three address bytes (A23

– A0) and dummy cycles (configurable,

default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the

first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted

out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while

simultaneously the second bit is output on IO2, the third bit is output on IO1, etc.

The first byte addressed can be at any memory location. The address is automatically incremented after each

byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h

address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is termin ated

by driving CE# high (VIH).

If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is

ignored and will not have any effects on the current cycle.

IS25LP032D-RGLA3:P Datasheet(PDF) 42 Page - Integrated Silicon Solution, Inc