LP1115-01

Dec.-2019

www.lowpowersemi.com

Page 2 of 10

Preliminary Datasheet

LP1115

Functional Pin Description

Package Type

Pin Configurations

QFN-20

(Top View)

20

19

18

17

16

6

7

8

9

10

15

14

13

12

11

1

2

3

4

5

GND1

21(PAD)

EN2

PWM2

DRVH2 SW2 GND2 DRVL2 VCC2

PWM1 EN1 VCC1

FB

BGND

BEN

BVCC

BSW

BST2

DRVL1

DRVH1

SW1

BST1

Pin Description

Pin No.

Name

Description

1

BST2

Channel 2. Upper MOSFET Floating Bootstrap Supply.

2

DRVL1

Channel 1. Output Drive for the lower MOSFET.

3

DRVH1

Channel 1. Output Drive for the upper MOSFET.

4

SW1

Channel 1. Switch Node. Connect to the source of the upper MOSFET.

5

BST1

Channel 1. Upper MOSFET Floating Bootstrap Supply.

6

PWM1

Channel 1. Logic-Level Input. This pin has primary control of the drive outputs.

7

EN1

Channel 1. Output Disable. When low, normal operation is disabled forcing DRVH1 and DRVL1 low.

8

VCC1

Channel 1. Input Supply. A 1μF ceramic capacitor should be connected from this pin to GND1.

9

FB

Boost. Regulation Feedback Input.

10

BGND

Boost. Ground.

11

BSW

Boost. Switch Node.

12

BVCC

Boost. Power Supply pin.

13

BEN

Boost. Output Disable. When low, boost enter low current shutdown mode.

14

PWM2

Channel 2. Logic-Level Input. This pin has primary control of the drive outputs.

15

EN2

Channel 2. Output Disable. When low, normal operation is disabled forcing DRVH2 and DRVL2 low.

16

VCC2

Channel 2. Input Supply. A 1μF ceramic capacitor should be connected from this pin to GND2.

17

DRVL2

Channel 2. Output Drive for the lower MOSFET.

18

GND2

Channel 2. Power Ground. Should be closely connected to the source of the lower MOSFET.

19

SW2

Channel 2. Switch Node. Connect to the source of the upper MOSFET.

20

DRVH2

Channel 2. Output Drive for the upper MOSFET.

21(PAD)

GND1

Channel 1. Power Ground. Should be closely connected to the source of the lower MOSFET.