STM32F469 datasheet(34/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

AN4861

34/91

DocID029237 Rev 2

Figure 21. AHB masters concurrent access to SDRAM

External SDRAM/SRAM memory bus width

When locating the framebuffer in an external SDRAM/SRAM, the user should consider that

the external memory running frequency is around half or third of the system frequency. That

is the reason why the memory bandwidth should be considered as the bottleneck of the

whole graphic system.

One of the needed parameters for checking the display compatibility is the memory bus

width. For SDRAM, the user can use a 8-bit, 16-bit or 32-bit configuration.

As previously stated, the most complex to analyze is the use case when the framebuffer is

placed in an external memory:

The masters concurrent access on the same external memory leads to more latency and

impacts its throughput.

Determining pixel clock and LTDC required bandwidth

Pixel clock computation

The pixel clock is a key parameter for checking display size compatibility with a specific

hardware configuration.

In order to get the typical pixel clock of display, refer to the display’s datasheet. The

computed pixel clock should respect the display’s specifications.

STM32F469 Datasheet(PDF) 34 Page - STMicroelectronics