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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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845GL Datasheet(PDF) 61 Page - Intel Corporation |
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845GL Datasheet(HTML) 61 Page - Intel Corporation |
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61 / 193 page  Intel® 82845G/82845GL/82845GV GMCH Datasheet 61 Register Description 3.5.1.17 DRA —DRAM Row Attribute Register (Device 0) Address Offset: 70–71h (72–77h Reserved) Default Value: 00h Access: R/W Size: 8 bits The DRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of rows. Each nibble of information in the DRA registers describes the page size of a pair of rows: Row0, 1: 70h Row2, 3: 71h 76 432 0 R Row Attribute for Row 1 R Row Attribute for Row 0 76 432 0 R Row Attribute for Row 3 R Row Attribute for Row 2 Bit Description 7 Reserved. 6:4 Row Attribute for Odd-numbered Row. This field defines the page size of the corresponding row. 000 = 2 KB 001 = 4 KB 010 = 8 KB 011 = 16 KB Others = Reserved 3 Reserved. 2:0 Row Attribute for Even-numbered Row. This field defines the page size of the corresponding row. 000 = 2 KB 001 = 4 KB 010 = 8 KB 011 = 16 KB Others = Reserved |
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