845GL datasheet(97/193 Pages) INTEL

97 / 193 page

Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.3.9

HDR2—Header Type Register (Device 2)

Address Offset:

0Eh

Default Value:

00h

Access:

Size:

8 bits

This register contains the Header Type of the IGD.

3.5.3.10

GMADR —Graphics Memory Range Address Register (Device 2)

Address Offset:

−13h

Default Value:

00000008h

Access:

R/W, RO

Size:

32 bits

This register requests allocation for the IGD graphics memory. The allocation is for either 64 MB

or 128 MB and the base address is defined by bits [31:27,26].

Bit

Description

7:0

Header Code (H).

This is an 8-bit value that indicates the Header Code for the IGD.

00h = Single function device with a type 0 configuration space format.

Bit

Description

31:27

Memory Base Address—R/W.

Set by the operating system. These bits correspond to address

signals [31:26].

128MB Address Mask—RO, R/W.

The operation of this bit is controlled via Device 0 register

GCCR. If the signal is low this bit is Read Only with a value of 0, indicating a memory range of

128 MB. If the signal is high, this bit becomes R/W, indicating a memory range of 64 MB (where

system software will program the bit to the appropriate address bit value).

25:4

Address Mask—RO.

Hardwired to zeros to indicate (at least) a 32-MB address range.

Prefetchable Memory—RO.

Hardwired to 1 to enable prefetching.

2:1

Memory Type—RO.

Hardwired to 0 to indicate 32-bit address.

Memory/IO Space—RO.

Hardwired to 0 to indicate memory space.

845GL Datasheet(PDF) 97 Page - Intel Corporation

845GL Datasheet(HTML) 97 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL