CS61584A datasheet(35/54 Pages) CIRRUS

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CS61584A

DS261PP5

10.10 Pause-DR State

The pause state allows the test controller to tempo-

rarily halt the shifting of data through the test data

TDO. For example, this state could be used to al-

low the tester to reload its pin memory from disk

during application of a long test sequence. The test

data register selected by the current instruction re-

tains its previous value and the instruction does not

change during this state. The controller remains in

this state as long as J-TMS is low. When J-TMS

goes high and a rising edge is applied to J-TCK, the

controller moves to the Exit2-DR state.

10.11 Exit2-DR State

This is a temporary state. While in this state, if J-

TMS is held high, a rising edge applied to J-TCK

causes the controller to enter the Update-DR state,

which terminates the scanning process. If J-TMS is

held low and a rising edge is applied to J-TCK, the

controller enters the Shift-DR state. The test data

its previous value and the instruction does not

change during this state.

10.12 Update-DR State

The Boundary Scan Register is provided with a

latched parallel output to prevent changes while

data is shifted in response to the EXTEST and

SAMPLE/PRELOAD instructions. When the TAP

controller is in this state and the Boundary Scan

output of this register from the shift-register path

on the falling edge of J-TCK. The data held at the

latched parallel output changes only in this state.

All shift-register stages in the test data register se-

lected by the current instruction retain their previ-

ous value and the instruction does not change

during this state.

10.13 Select-IR-Scan State

This is a temporary controller state. The test data

its previous state. If J-TMS is held low and a rising

edge is applied to J-TCK when in this state, the

controller moves into the Capture-IR state, and a

scan sequence for the instruction register is initiat-

ed. If J-TMS is held high and a rising edge is ap-

plied to J-TCK, the controller moves to the Test-

Logic-Reset state. The instruction does not change

during this state.

10.14 Capture-IR State

In this controller state, the shift register contained

in the instruction register loads a fixed value of

"01" on the rising edge of J-TCK. This supports

fault-isolation of the board-level serial test data

path. Data registers selected by the current instruc-

tion retain their value and the instruction does not

change during this state. When the controller is in

this state and a rising edge is applied to J-TCK, the

controller enters the Exit1-IR state if J-TMS is held

high, or the Shift-IR state if J-TMS is held low.

10.15 Shift-IR State

In this state, the shift register contained in the in-

struction register is connected between J-TDI and

J-TDO and shifts data one stage towards its serial

output on each rising edge of J-TCK. The test data

its previous value and the instruction does not

change during this state. When the controller is in

this state and a rising edge is applied to J-TCK, the

controller enters the Exit1-IR state if J-TMS is held

high, or remains in the Shift-IR state if J-TMS is

held low.

CS61584A

DS261F1

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