CS61584A datasheet(45/54 Pages) CIRRUS

45 / 54 page

CS61584A

DS261PP5

Status

AIS1, AIS2 - Alarm Indication Signal [Host mode] (PLCC pins 15, 54; TQFP pins 6, 43)

The AIS indication goes high when the receiver detects 99.9% ones density in a 5.3 ms period (< 9

zeros in 8192 bits). The AIS indication returns low when the receiver detects

≥ 9 zeros in 8192 bits.

BPV1, BPV2 - Bipolar Violation [Host mode] (PLCC pins 12, 57; TQFP pins 3, 46)

The BPV indication goes high for one RCLK bit period when a bipolar violation is detected in the

received signal. Bipolar violations caused by B8ZS (or HDB3) zero substitutions are not flagged by the

BPV pin if the coder mode is enabled.

The BPV pin also goes high for one RCLK bit period on excessive zero events if EXZ = 1 (Control A

mode, the BPV pin goes high when 8 or more zeros are received. This functionality is disabled when

the device is configured for E1 operation.

LOS1 - Loss of Signal [Hardware mode and Host mode - serial port]

LOS2 - (PLCC pins 16, 53; TQFP pins 7, 42)

The LOS indication goes high when 175 ±15 consecutive zeros are received on the line interface, or

when the receive (RTIP/RRING) signal level drop below the receiver sensitivity of the device. The LOS

indication returns low when a minimum 12.5% ones density signal over 175 ±75 bit periods with no

more than 100 consecutive zeros is received.

Test

J-TCK - JTAG Test Clock (PLCC pin 51; TQFP pin 40)

Data on pins J-TDI and J-TDO is valid on the rising edge of J-TCK. When J-TCK is stopped low, all

JTAG registers remain unchanged.

J-TMS - JTAG Test Mode Select (PLCC pin 50; TQFP pin 39)

An active high signal on J-TMS enables the JTAG serial port. This pin has an internal pull-up resistor

and may be unconnected to float high or tied low while the JTAG interface is not active.

J-TDI - JTAG Test Data In (PLCC pin 19; TQFP pin 10)

JTAG data is shifted into the device on this pin. This pin has an internal pull-up resistor. Data must be

stable on the rising edge of J-TCK.

J-TDO - JTAG Test Data Out (PLCC pin 17; TQFP pin 8)

JTAG data is shifted out of the device on this pin. This pin is active only when JTAG testing is in

progress. J-TDO will be updated on the falling edge of J-TCK.

CS61584A

DS261F1

CS61584A Datasheet(PDF) 45 Page - Cirrus Logic