Time (50 msec/Div)

D004

Current waveform

14

OPA607

SBOS981 – OCTOBER 2019

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Figure 8. Low-Side Current-Sensing Waveform in a BLDC Motor Control

An ADC capturing the data at 500 kSPS puts out a sampled data one time every 2 µs. Because the minimum

current pulse duration while running at a 5% duty cycle is 2.5 µs, a 500-kSPS sampling rate ADC is sufficient for

this BLDC current-sensing application. The ADS7042 is a low-power, 12-bit, 1-MSPS, SAR ADC. The ADS7042

is operated at 500 kSPS via SCLK at a frequency of 12.5 MHz, which is a standard clock frequency available for

SPI communications. For an ADC running at a sampling rate of 500 kSPS on a clock of 12.5 MHz, the bandwidth

of the op amp required to drive such an ADC is approximately 2.7 MHz. See the TI precision lab videos on

driving SAR ADCs to understand the underlying calculation. The OPA607 has a GBW of 50 MHz. With a gain of

20 V/V, the effective bandwidth available with the OPA607 comes out to approximately 2.5 MHz, making the

device the most suitable, cost-optimized amplifier for this application. The RC (240 Ω and 688 pF in Figure 7)

charge bucket designed at the input of the SAR ADC is also derived from the calculations provided in the SAR

ADC precision lab videos. The fundamental concept behind the design of this charge bucket is to ensure that the

acquisition capacitor is charged up to the required final voltage within the acquisition window of the ADC.

The ADS7042 samples at 500 kSPS with a 12.5-MHz clock, which translates to a conversion time of 1 µs out of

the total time period of 2 µs (1 / 500 kHz). These calculations for different sampling rates and clock frequencies

can be found in the ADS7042 data sheet. With the conversion time of 1 µs out of the 2 µs, the OPA607 is left

with 1 µs to settle to the required accuracy of 0.1%. Because the full-scale voltage is assumed to be 3 V, an

accuracy of 0.1% translates to a maximum allowable error voltage of 3 mV. Thus, the OPA607 must settle to ±3

mV of its final intended value within 1 µs.

Figure 9 shows the TINA™ simulation plots for the OPA607 driving the ADS7042. Input voltage (red) is the

signal swing across the shunt resistance and the error signal (blue) is representative of the % error in the output

sharply transits from its lowermost point to the uppermost point. This transition can be considered as a short-

circuit event or step increase in current resulting from a sudden metal-oxide-semiconductor field-effect transistor

(MOSFET) switching. The output (black) waveform tries to follow the high slew rate input signal but is limited by

the effective bandwidth of the op amp used. Thus, a higher bandwidth op amp results in the output being able to

more closely track the input. The difference between the output and input is represented by the error waveform

and the goal of the design is to reduce this error to less than 0.1% within the acquisition window of the ADC. The

acquisition window of the ADC is shown in the yellow highlighted regions of Figure 9. Thus the % error signal

(blue) must settle down to less than 0.1% before the end of this 1-µs window (within the yellow marked region).

As illustrated in Figure 9, the error signal comfortably settles to the final value with an error % of –0.025%, which

is well within the required 0.1% accuracy. Thus, the OPA607 settles to 0.1% accuracy within 1 µs with a worst-

case, 0-V to 3-V full-scale transient output that is also in a gain configuration of 20 V/V. The OPA607 enables

single-sample settling for the ADS7042 running on a 12.5-MHz clock with 500 kSPS, thus making the device a

very cost-optimized, single amplifier solution.

Figure 10 gives the DC transfer characteristics of the circuit in Figure 7. As per the parameters from Table 2 the

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