CS61880 datasheet(44/70 Pages) CIRRUS

44 / 70 page

CS61880

DS450PP3

16.1 TAP Controller

The TAP Controller is a 16 state synchronous state

machine clocked by the rising edge of TCK. The

TMS input governs state transitions as shown in

Figure 15. The value shown next to each state tran-

sition in the diagram is the value that must be on

TMS when it is sampled by the rising edge of TCK.

16.1.1 JTAG Reset

TRST resets all JTAG circuitry.

16.1.2 Test-Logic-Reset

The test-logic-reset state is used to disable the test

logic when the part is in normal mode of operation.

This state is entered by asynchronously asserting

TRST or forcing TMS High for 5 TCK periods.

16.1.3 Run-Test-Idle

The run-test-idle state is used to run tests.

16.1.4 Select-DR-Scan

This is a temporary controller state.

16.1.5 Capture-DR

In this state, the Boundary Scan Register captures

input pin data if the current instruction is EXTEST

or SAMPLE/PRELOAD.

16.1.6 Shift-DR

In this controller state, the active test data register

connected between TDI and TDO, as determined

by the current instruction, shifts data out on TDO

on each rising edge of TCK.

16.1.7 Exit1-DR

This is a temporary state. The test data register se-

lected by the current instruction retains its previous

value.

parallel latched

output

Boundary Scan Data Register

Device ID Data Register

Bypass Data Register

Instruction (shift) Register

TAP

Controller

parallel latched output

TDI

TCK

Digital output pins

Digital input pins

JTAG BLOCK

MUX

TDO

TMS

Figure 14. Test Access Port Architecture

CS61880 Datasheet(PDF) 44 Page - Cirrus Logic

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