LS1022A datasheet(16/71 Pages) FREESCALE

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Architecture

TWR-LS1021A Reference Manual, Rev. 0

Freescale Semiconductor

2-1

Chapter 2

Architecture

The TWR-LS1021A architectures are primarily determined by the processor, and by the need to evaluate

as many of its features as possible, maximizing testability without impacting the ability to deliver an easily

usable off-the-shelf software development platform.

Table 2-1 lists the major functional blocks of each processor and the associated circuitry for evaluating

them. Included is a reference to specific board-related setup and programming instructions.

Table 2-1. Processor functional blocks

Signal Group

Details

Configuration

Processor

Section 2.1, “Processor”n/a

Power

Section 2.2, “Power”n/a

Deep Sleep Control

Section 2.3, “Deep sleep control”n/a

Reset

Section 2.4, “Reset”n/a

Configuration

Section 2.5, “Device configuration”n/a

Clock

Section 2.6, “Clocks”n/a

Memory Controllers

Section 2.7, “Memory controllers”n/a

SerDes Ports

Section 2.8, “SerDes port”

Section 2.8.4, “SerDes configuration and setup”

Ethernet

Section 2.9, “Ethernet controllers”n/a

EMI Ports

Section 2.10, “Ethernet management interface”n/a

IEEE 1588

Section 2.10.1, “IEEE-1588™ support”n/a

USB

Section 2.11, “USB interface”

Section 2.11.1, “USB configuration and setup”

Local Bus

Section 2.12, “Local bus”n/a

DIU

Section 2.13, “2D ACE - Display Controller Port

n/a

I2C

Section 2.14, “I2C”n/a

SPI

Section 2.15, “SPI interface”

Section 2.15.1, “SPI configuration and setup”

SDHC

Section 2.16, “SDHC interface”n/a

Interrupts

Section 2.17, “Interrupt controller”n/a

UART

Section 2.18, “Serial ports”

Section 2.18.1, “UART configuration and setup”

Audio

Section 2.19, “Audio port”n/a

JTAG Port

Section 2.20, “JTAG port”n/a

GPIO

Section 2.21, “GPIO pins”n/a

LEDs

Section 2.22, “Monitoring LEDs”n/a

MBED

Section 2.23, “MBED”n/a

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