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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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LS1022A Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc |
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LS1022A Datasheet(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 71 page  Architecture TWR-LS1021A Reference Manual, Rev. 0 2-8 Freescale Semiconductor Figure 2-6. Clock architecture 2.6.1 SYSCLK / DDRCLK SYSCLK and DDRCLK are provided by an IDT 6V49205BNLGI, a programmable frequency synthesizer with hardware presets. The device is strapped to provide 100 MHz to SYSCLK and 67 MHz to DDRCLK during power up. LS1021A requires 64 MHz to 100 MHz for both SYSCLK and DDRCLK. Spread Spectrum Clocking (SSC) options are supported for SYSCLK and DDRCLK by SMBUS. Because SSC reduces the clock rate, reducing the performance somewhat, it is not a preferred operating mode. Table 2-4. SYSCLK frequency options FS[0:1] SYSCLK Notes 0 0 66.67 MHz n/a 0 1 80 MHz n/a 1 0 100.00 MHz default 1 1 83.33 MHz n/a Table 2-5. DDRCLK frequency options DDRCLK pin DDRCLK Notes pull-up 66.67 MHz n/a pull-down 100.00 MHz Default on TWR-LS1021A |
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