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LM2502 Datasheet(PDF) 17 Page - National Semiconductor (TI) |
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LM2502 Datasheet(HTML) 17 Page - National Semiconductor (TI) |
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17 / 27 page ![]() Functional Description (Continued) CPU MODE — READ — m68 TABLE 6. READ — 6800 µP Interface Parameters No. Parameter Min Typ Max Units T1 MasterIN Set Up Time (A/D, R/W*) and Data On Time 20 ns T2 MasterIN Hold Time (A/D, R/W*) and Data Off Time 15 ns T3 Master Master Latency 5 MC Cycles T4 Slave Slave Latency 6 MC Cycles T5 Slave ChipSelect* Delay 1 MC Cycles T6 Slave ChipSelect Low Pulse Width 6 MC Cycles T7 Slave Data Set Up Time 5 ns T8 Slave Data Hold Time 15 ns T9 Slave Slave Read Latency 4 MC Cycles T10 Master MST Read Latency and INTR Delay 12 MC Cycles T11 Master Data Delay 18.6 ns T12 MasterOUT Data Valid after Strobe 15 ns T13 MasterOUT CS* or E active pulse width 20 ns T14 MasterOUT INTR De-assert 5 MC Cycles 20093311 FIGURE 14. READ — 6800 µP Interface www.national.com 17 |
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