Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SUPPLY CURRENT

I

DD

Total Supply

Current — Enabled

Conditions: MC = 76.8

MHz, MD = 1010-0101

pattern (worse case toggle,

rail-to-rail levels), CLK =

19.2 MHz (4X) (Note 7)

Master

V

DDIO

15

220

µA

V

14

25

mA

Slave, C

V

DDIO

1.5

9.0

mA

V

9.0

13.0

mA

Total Supply

Current — Enabled

Conditions: MC = 20 MHz,

MD = 1010-0101 pattern

(worse case toggle,

rail-to-rail levels), CLK = 5

MHz (4X)

Master

V

10

µA

V

5mA

Slave, C

V

1mA

V

4mA

I

DDZ

Supply Current — Disabled

Power_Down Mode, PD* = 0V

1

10

µA

Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

PARALLEL BUS TIMING

t

SET

Set Up Time, Data to Edge

Inputs

5

ns

t

HOLD

Hold Time, Edge to Data

5

ns

t

RISE

Rise Time

Figure 2, Outputs,

C

Edge sensitive

outputs tested

only:

V

2

7

14

ns

V

1

2

10

ns

t

FALL

Fall Time

V

2

6

14

ns

V

1

2

10

ns

CLK

DC

Output Clock Duty Cycle

50

%

Parallel Bus Timing - See Figures 13, 14, 15, 16 and

Table 5, Table 6, Table 7, and Table 8

SERIAL BUS TIMING

t

DVBC

Data Valid before Clock

Master-to-Slave

(Note 5)

2.0

ns

t

DVAC

Data Valid after Clock

0.5

ns

POWER UP TIMING(Note 5)

t

0

Master PLL Lock Counter

Figure 6

4096

CLK

cycles

t

1

MC Pulse Width Low

(Master)

11

CLK

cycles

t

2

MC Pulse Width HIGH

(Master)

11

CLK

cycles

t

3

MC Pulse Width Low

(Master)

11

CLK

cycles

t

4

CLK-Out Delay (Slave)

7

MC

cycles

t

5

Power Up Total delay

(t

4133

CLK

cycles

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