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THCV235 Datasheet(PDF) 7 Page - California Eastern Labs |
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THCV235 Datasheet(HTML) 7 Page - California Eastern Labs |
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7 / 68 page ![]() THCV235_THCV236_Rev.3.40_E Copyright©2016 THine Electronics, Inc. THine Electronics, Inc. 7/68 Security E BET/GPIO1 55 BO BET : Field BET entry when PDN1=0 or Sub-Link is active and Low Speed Data Bridge Mode(PDN1=1, SUBMODE=1). 0 : Normal Operation 1 : Field BET Operation GPIO1 : General Purpose Input/Output when SUBMODE=0. GPIO1 has Open-Drain Output buffer, it must be connected with a pull-up resistor to VDD. SSEN/GPIO0 54 BO SSEN : Spread Spectrum Clock Generator(SSCG) Enable when PDN1=0 or Sub-Link is active and Low Speed Data Bridge Mode(PDN1=1, SUBMODE=1). 0 : SSCG Disable 1 : SSCG Enable GPIO0 : General Purpose Input/Output when SUBMODE=0. GPIO0 has Open-Drain Output buffer, it must be connected with a pull-up resistor to VDD. CLKIN 26 I Clock Input D31-D0 53,52,47-42, 39-33,31-27, 24-17,15-12 I Pixel Data Input DE 51 I DE Input HSYNC 50 I HSYNC Input VSYNC 48 I VSYNC Input RF/BETOUT 6 B RF : Input Clock Triggering edge select. See Figure 19. 0 : Falling Edge 1 : Rising Edge BETOUT : Field BET Result Output when Field BET mode LFSEL 3 I Low Frequency mode select 0 : Low Frequency mode Disable 1 : Low Frequency mode Enable PDN1 2 IL Sub-Link Power Down 0 : Power Down. Main-Link setting by external pin 1 : Normal Operation. Main-Link Setting by 2-wire serial I/F PDN0 1 IL Main-Link Power Down 0 : Power Down 1 : Normal Operation TEST2 5 I Test pin. Must be tied to Ground for normal operation. TEST1 4 IL Test pin. Must be tied to Ground for normal operation. CAPOUT 56 PWR Decoupling Capacitor Pin, 1.2V output. CAPINA 61 PWR Reference Input for Analog Circuit. Must be tied to CAPOUT. CAPINP 62 PWR Reference Input for Analog Circuit. Must be tied to CAPOUT. VDD 49,41,32,25,16 PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O AVDD 40 PWR 1.7-3.6V Analog Power Supply Pin for LDO EXPGND 65 GND Exposed Pad Ground. Must be tied to the PCB ground plane through an array of vias. CO : CML Output buffer , CB : CML Bi-directional buffer I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer PWR : Power supply , GND : Ground |
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