AM652X datasheet(245/299 Pages) TI1

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245

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

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Two Real-Time Transfer Units (RTU_PRU0 and RTU_PRU1), each with

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8KB program memory with ECC

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16KB Broadside (BS) RAM

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MAC (Multiplier with optional Accumulation)

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CRC32/16 HW accelerator

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Byte Swap, for Little/Big Endian conversion

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Two instances of SUM32

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Task Manager

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XFR2TR, for accelerating the internal memory copy of worklist from TR

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Supports 128-bit wide PSI-L RX/TX port for streaming access through NAVSS0

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Scratchpad Memory (SPAD) with 4 banks of 30 x 32-bit registers

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64KB Shared general purpose memory RAM with ECC (signified Data RAM2), shared between PRU0

and PRU1

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Two 8KB Data Memories with ECC (signified Data RAM0 and Data RAM1)

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Two 256-bit VBUSM Master Ports:

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Separate port for each PRUn/RTU_PRUn (where n = 0 or 1)

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Optional address translation for PRUn (where n = 0 or 1) transactions to External Host

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16 Software Events generated by 2 PRUs

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Two Real-Time Ethernet ports (MII_G_RT1 and MII_G_RT2) configurable to connect to each PRUn

(where n = 0 or 1) to support multiple industrial communication protocols.

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Each of the Ethernet ports can be configured as MII/RGMII/SGMII ports

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NOTE: SGMII mode is supported only for PRU_ICSSG2 instance

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Two Industrial Ethernet Peripheral's (IEP0/IEP1) to manage/generate Industrial Ethernet functions such

as time stamping.

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Each of the Industrial Ethernet 64-bit timers support 10 capture and 16 compare events along with

slow and fast compensation.

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Supports up to 4 sets of 3 phased motor control with 12 primary and 12 complimentary

programmable PWM outputs.

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Up to 9 safety events with optional external trip IO per PWM set with hardware glitch filter.

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One MDIO port to control external Ethernet PHY

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One Enhanced Capture Module (ECAP0)

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16550-compatible UART with a dedicated 192MHz clock to support 12-Mbps PROFIBUS®

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Interrupt Controller (INTC)

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Up to 64 internal events, generated by modules, internal to the PRU_ICSSG

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Up to 96 external events, generated by the system

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Supports up to 20 interrupt channels

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Generation of 20 Host interrupts:

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2 Host interrupts to PRU0 and PRU1

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2 Host interrupts to RTU_PRU0 and RTU_PRU1

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8 Host interrupts, exported from the PRU_ICSSG for signaling the Arm interrupt controllers

(pulse and level provided)

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8 Host Interrupts for the Task Managers

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Each system event can be enabled and disabled

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Each host event can be enabled and disabled

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Hardware prioritization of events

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One 32-bit VBUSP slave (target) port for memory mapped register and internal memories access

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Flexible power management support

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Integrated 32-bit Interconnect

AM652X Datasheet(PDF) 245 Page - Texas Instruments

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