ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319

FN7549 Rev 3.00

Page 18 of 23

August 18, 2015

Reading After Conversion Mode, with EOC

In this mode (Figure 33), after CNV is asserted Low to start input

acquisition, a data exchange is executed by SCLK during the

Acquisition period. CNV is asserted High briefly to initiate a

Conversion, forcing SDO to a high-impedance state. SDO returns

HIGH when CNV is asserted Low during the entire conversion period.

At the end of conversion, the device asserts SDO Low to indicate

that the conversion is complete. This may be used as an interrupt

to start the Acquisition phase. It should be noted (as indicated in

Figure 33) that an additional pulse on CNV is required at the end

of conversion to take the part back to Acquisition from Idle state.

As discussed in section “Reading After Conversion Mode Without

throughput at slower SPI clock rates.

Reading During Conversion Mode, with EOC

From Idle, a falling edge on CNV initiates the Acquisition mode,

and then a rising edge initiates a Conversion. After the

conversion is initiated, CNV is asserted Low once again. Data

exchange across SDI and SDO can proceed while CNV is Low,

minimize the effects of digital noise on sensitive portions of the

conversion. In this mode, an additional pulse is required on SCLK

after the completion of the data exchange, to transition SDO to

the high-impedance state. Later, SDO is asserted low by the

device indicating end of conversion. The device then returns to

Idle. The falling edge of SDO may be used as an interrupt to start

the Acquisition phase (see Figure 34).

Reading Spanning Conversion Mode, with EOC

After initiating an Acquisition by bringing CNV Low, the user

begins exchanging data as previously mentioned, until CNV is

asserted High to initiate a conversion and SDO returns to a

high-impedance state, interrupting the exchange. And, after CNV

is returned Low, SDO will return to the state prior to the CNV

pulse in order to avoid losing data interrupted by the conversion

pulse (see Figure 35). The user should take care to observe the

sensitive portions of conversion. After completion of the data

exchange, an additional pulse on SCLK forces SDO to a

high-impedance state. At the end of conversion, the device

asserts SDO Low indicating the end of conversion. The device

then returns to Idle, waiting for a pulse on CNV to initiate a new

Acquisition cycle.

Accessing the Configuration Register During

Data Readback

The Configuration Register contains the channel address of the

current conversion data. The contents can be accessed during a

normal data output sequence by continuing to clock data from

SDO if the register readback mode is enabled. Both 12-bit output

data words and the 16-bit configuration word are output in 28

SCLK periods, as shown in Figure 36, which demonstrates an

example sequence. Note that SDO goes into the high-impedance

state when CNV is High. The Configuration Register can be read

during any Read Sequence by generating the additional SCLKs,

with the restriction that the sequence must be completed prior to

the end of the current conversion. This will prevent loss of data

due to overwriting of the new conversion data into the output and

configuration registers.

FIGURE 33. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE WITH EOC ON SDO OUTPUT

Acq.

Acquisition

CNV

SCLK

SDI

SDO

MSB

MSB-1

D15

D14

. . .

. . .

D1

LSB

ADC STATE

Idle

Power-Up

Acquisition

Conversion

Idle

Conversion N+1

Configuration N+1

Conversion Result N-1

MSB

MSB-1

D15

D14

. . .

. . .

LSB

Configuration N+2

Conversion Result N

Conversion

Idle

Hi-Z State

Conversion N

D5

D4

D5

D4