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ISL26310 Datasheet(PDF) 17 Page - Renesas Technology Corp

No. de pieza ISL26310
Descripción Electrónicos  12-bit, 125kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels
PDF  23 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL26310 Datasheet(HTML) 17 Page - Renesas Technology Corp

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ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319
FN7549 Rev 3.00
Page 17 of 23
August 18, 2015
FIGURE 30. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE, WITHOUT EOC
FIGURE 31. TIMING DIAGRAM FOR READING DURING CONVERSION MODE, WITHOUT EOC
FIGURE 32. TIMING DIAGRAM FOR READING SPANNING CONVERSION MODE, WITHOUT EOC
Acq.
Acquisition
CNV
SCLK
SDI
SDO
MSB
MSB-1
D15
D14
. . .
. . .
D1
LSB
D5
D4
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Idle
tACQ
tSCLK
tSDO_V
tSCLKL
Conversion N+1
Configuration N+1
Conversion Result N-1
tSCLKH
MSB
MSB-1
D15
D14
. . .
. . .
LSB
Configuration N+2
Conversion Result N
Conversion
Idle
tSDOZ_D
tCNV_SCLK
tSDI_H
tSDI_SU
Hi-Z State
Conversion N
D5
D4
Idle
CNV
SCLK
SDI
SDO
D15
D14
. . .
. . .
D14
. . .
. . .
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Idle
Acquisition
Conversion
tACQ
tSCLK
tCNV_CLK
tSCLKL
tDATA
tCNV
Conversion N
Conversion N+1
Configuration N+1
Conversion Result N-1
Configuration N+2
Conversion Result N
tSCLKH
MSB
MSB-1
D1
LSB
MSB
MSB-1
D1
tSDO_V
tSDI_H
tSDI_SU
Hi-Z State
D5
D4
D5
D4
Idle
Idle
CNV
SCLK
SDI
SDO
D15
D14
. . .
D4
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Acquisition
Conversion
tACQ
tSCLK
tCNV_SCLK
tSCLKL
tDATA
tCNV
Conversion N
Conversion N+1
Configuration N+1
Conversion Result N-1
Configuration N+2
Conversion Result N
tSCLKH
D12
MSB
MSB-1
D1
LSB
D13
Hi-Z State
MSB
MSB-1
D1
tSDO_V
tSDI_H
tSDI_SU
D15
D14
D4
. . .
MSB-1 MSB-2
MSB-1 MSB-2
. . .
Note: Transition from Acquisition to Conversion mode may occur after any integer number of clock cycles (provided that the minimum tACQ is satisfied).
. . .
D12
D13



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