LMH6574 datasheet(13/15 Pages) NSC

13 / 15 page

Other Applications (Continued)

output under capacitive loading. Capacitive loads of

5 to 120 pF are the most critical, causing ringing, frequency

response peaking and possible oscillation. The chart “Sug-

gested R

OUT vs. Cap Load” gives a recommended value for

selecting a series output resistor for mitigating capacitive

loads. The values suggested in the charts are selected for

0.5 dB or less of peaking in the frequency response. This

gives a good compromise between settling time and band-

width. For applications where maximum frequency response

is needed and some peaking is tolerable, the value of R

OUT

can be reduced slightly from the recommended values.

LAYOUT CONSIDERATIONS

Whenever questions about layout arise, use the evaluation

board as a guide. The LMH730276 is the evaluation board

supplied with samples of the LMH6574. To reduce parasitic

capacitances, ground and power planes should be removed

near the input and output pins. For long signal paths con-

trolled impedance lines should be used, along with imped-

ance matching elements at both ends. Bypass capacitors

should be placed as close to the device as possible. Bypass

capacitors from each rail to ground are applied in pairs. The

larger electrolytic bypass capacitors can be located farther

from the device, the smaller ceramic capacitors should be

placed as close to the device as possible. In Figure 1, the

capacitor between V

+ and V− is optional, but is recom-

mended for best second harmonic distortion. Another way to

enhance performance is to use pairs of 0.01µF and 0.1µF

ceramic capacitors for each supply bypass.

POWER DISSIPATION

The LMH6574 is optimized for maximum speed and perfor-

mance in the small form factor of the standard SOIC pack-

age. To ensure maximum output drive and highest perfor-

mance, thermal shutdown is not provided. Therefore, it is of

utmost importance to make sure that the T

JMAX is never

exceeded due to the overall power dissipation.

Follow these steps to determine the Maximum power dissi-

pation for the LMH6574:

Calculate the quiescent (no-load) power: P

AMP =ICC*

S), where VS =V

+ -V−.

Calculate the RMS power dissipated in the output stage:

D (rms) = rms ((VS -VOUT)*IOUT), where VOUT and

OUT are the voltage across and the current through the

external load and V

S is the total supply voltage.

Calculate the total RMS power: P

T =PAMP +PD.

The maximum power that the LMH6574 package can dissi-

pate at a given temperature can be derived with the following

equation:

MAX = (150˚ – TAMB)/

JA, where TAMB = Ambient tempera-

ture (˚C) and

JA = Thermal resistance, from junction to

ambient, for a given package (˚C/W). For the SOIC package

JA is 130 ˚C/W.

20119724

FIGURE 6. Decoupling Capacitive Loads

20119715

FIGURE 7. Suggested R

OUT vs. Capacitive Load

20119714

FIGURE 8. Frequency Response vs. Capacitive Load

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