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LMH6574 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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LMH6574 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 15 page ![]() Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 4) Human Body Model 2000V Machine Model 200V Supply Voltage (V + −V−) 13.2V I OUT (Note 3) 130 mA Signal & Logic Input Pin Voltage ±(V S+0.6V) Signal & Logic Input Pin Current ±20 mA Maximum Junction Temperature +150˚C Storage Temperature Range −65˚C to +150˚C Soldering Information Infrared or Convection (20 sec) 235 ˚C Wave Soldering (10 sec) 260 ˚C Operating Ratings (Note 1) Operating Temperature −40 ˚C to 85 ˚C Supply Voltage Range 6V to 12V Thermal Resistance Package ( θ JA)( θ JC) 14-Pin SOIC 130˚C/W 40˚C/W ±5V Electrical Characteristics V S = ±5V, RL = 100 Ω,A V=2 V/V, TJ=25 ˚C, Unless otherwise specified. Bold numbers specify limits at temperature extremes. Symbol Parameter Conditions (Note 2) Min Typ Max Units Frequency Domain Performance SSBW −3 dB Bandwidth V OUT = 0.5VPP 500 MHz LSBW –3 dB Bandwidth V OUT =2VPP 400 MHz .1 dBBW 0. 1 dB Bandwidth V OUT = 0.25VPP 150 MHz DG Differential Gain R L = 150 Ω, f=4.43 MHz 0.02 % DP Differential Phase R L = 150 Ω, f=4.43MHz 0.05 deg XTLK Channel to Channel Crosstalk All Hostile, 5MHz −85 dB Time Domain Response TRS Channel to Channel Switching Time Logic transition to 90% output 8 ns Enable and Disable Times Logic transition to 90% or 10% output. 10 ns TRL Rise and Fall Time 4V Step 2.4 ns TSS Settling Time to 0.05% 2V Step 17 ns OS Overshoot 2V Step 5 % SR Slew Rate 4V Step 2200 V/µs Distortion HD2 2 nd Harmonic Distortion 2V PP , 5 MHz −68 dBc HD3 3 rd Harmonic Distortion 2V PP , 5 MHz −84 dBc IMD 3 rd Order Intermodulation Products 10MHz, Two tones 2Vpp at output −80 dBc Equivalent Input Noise VN Voltage >1MHz, Input Referred 5 nV ICN Current >1MHz, Input Referred 5 pA/ Static, DC Performance CHGM Channel to Channel Gain Difference DC, Difference in gain between channels ±0.005 ±0.032 ±0.035 % VIO Input Offset Voltage (Note 5) V IN =0V 1 ±20 ±25 mV DVIO Offset Voltage Drift 30 µV/˚C IBN Input Bias Current (Notes 7, 5) V IN =0V −3 ±5 ±5.6 µA DIBN Bias Current Drift 11 nA/˚C Inverting Input Bias Current Pin 12, Feedback point, V IN =0V −7 ±10 ±13 PSRR Power Supply Rejection Ratio (Note 5) DC, Input referred 47 45 54 dB www.national.com 2 |
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