PIC16F74-ESLASHML datasheet(99/174 Pages) MICROCHIP

99 / 174 page

 2002 Microchip Technology Inc.

DS30325B-page 97

PIC16F7X

FIGURE 12-6:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH

RC NETWORK)

PIE2

---- ---0

---- ---u

PCON

---- --qq

---- --uu

PR2

73747677

1111 1111

SSPSTAT

--00 0000

--uu uuuu

SSPADD

73747677

0000 0000

uuuu uuuu

TXSTA

73747677

0000 -010

uuuu -uuu

SPBRG

0000 0000

uuuu uuuu

ADCON1

---- -000

---- -uuu

PMDATA

0--- 0000

u--- uuuu

PMADR

73747677

xxxx xxxx

uuuu uuuu

PMDATH

xxxx xxxx

uuuu uuuu

PMADRH

xxxx xxxx

uuuu uuuu

PMCON1

1--- ---0

1--- ---u

TABLE 12-6:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Devices

Power-on Reset,

Brown-out Reset

MCLR Reset,

WDT Reset

Wake-up via WDT or

Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition,

= reserved, maintain clear

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

3: See Table 12-5 for RESET value for specific condition.

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

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