ACE24AC02A1

Two-wire Serial EEPROM

VER 1.4

4

B.

Start Conditions

With SCL ≥ VIH, a SDA transition from high to low is interpreted as a start condition. All valid

commands must begin with a start condition.

C.

Stop Condition

With SCL ≥ VIH, a SDA transition from low to high is interpreted as a stop condition. All valid read or

write commands end with a stop condition. The device goes into the standby mode if it is after a read

command. A stop condition after page or byte write command will trigger the chip into the standby

mode after the self-timed internal programming finish.

D.

Acknowledge

The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The

EEPROM acknowledge the data or address by outputting a "0" after receiving each word. The

acknowledge signal occurs on the 9th serial clock after each word.

E.

Standby Mode

The EEPROM goes into low power standby mode after a fresh power up, after receiving a stop bit in

read mode, or after completing a self-time internal programming operation.

Figure 3: Timing Diagram For Start And Stop Conditions

Figure 4: Timing Diagram For Output Acknowledge