ACE24AC1024DDPTH datasheet(4/13 Pages) ACE

4 / 13 page

ACE24AC1024D

Two-wire Serial EEPROM

VER 1.2

Memory Organization

The ACE24AC1024D devices have 512 pages respectively. Since each page has 256 bytes, random

word addressing to ACE24AC1024D will require 17 bits data word addresses respectively.

Device Operation

(A)

Serial Clock And Data Transitions

The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when

Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a start or stop condition

as described below.

(B)

Start Condition

With SCL VIH, a SDA transition from high to low is interpreted as a start condition. All valid commands

must begin with a start condition.

(C)

Stop Condition

With SCL VIH, a SDA transition from low to high is interpreted as a stop condition. All valid read or

write commands end with a stop condition. The device goes into the standby mode if it is after a read

command. A stop condition after page or byte write command will trigger the chip into the standby

mode after the self-timed internal programming finish (see Figure 1).

(D)

Acknowledge

The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The

EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The

acknowledge signal occurs on the 9

th serial clock after each word.

(E)

Standby Mode

The EEPROM goes into low power standby mode after a fresh power up, after receiving a stop bit in

read mode, or after completing a self-time internal programming operation.

Figure 1: Timing diagram for start and stop conditions

ACE24AC1024DDPTH Datasheet(PDF) 4 Page - ACE Technology Co., LTD.