AD652BQ datasheet(21/29 Pages) AD

21 / 29 page

AD652

Rev. C | Page 20 of 28

SVFC Demultiplexer

The demultiplexer needed to separate the combined signals is

shown in Figure 30. A phase-locked loop drives another 4-phase

clock chip to lock onto the reconstructed clock signal. The sync

pulses are distinguished from the data pulses by their shorter

duration. Each falling edge on the multiplex input signal

triggers the one-shot; at the end of this one-shot pulse, the

multiplex input signal is sampled by a D-type flip-flop. If the

signal is high, the pulse was short (a sync pulse) and the Q

output of the D-flop goes low. The D-flop is cleared a short time

(two gate delays) later, and the clock is reconstructed as a

stream of short, low-going pulses. If the multiplex input is a data

pulse, then the signal will still be low and no pulse will appear at

the reconstructed clock output when the D-flop samples at the

end of the one-shot period. See Figure 29.

If it is desired to recover the individual frequency signals, the

multiplex input is sampled with a D-flop at the appropriate

time, as determined by the rising edge of the various phases

generated by the clock chip. These frequency signals can be

counted as a ratio relative to the reconstructed clock, so it is not

even necessary for the transmitter to be crystal-controlled as

shown in Figure 30.

φ1

SYNC

φ2

φ3

DATA

φ4

φ2

φ3

φ4

1MULTIPLEX

OUTPUT

Figure 28. Multiplexer Waveforms

MULTIPLEX

INPUT

ONE SHOT

RECONSTRUCTED

CLOCK

φ1

(PHASE LOCKED TO

RECONSTRUCTED

CLOCK)

Figure 29. Demultiplexer Waveforms

0.1

µF

PHASE LOCK LOOP

MC4044

3.01k

Ω

719

Ω

+5V

φ4

φ3

φ1

+5V

φ2

TANK 1

TIM 9904A

4 PHASE CLOCK

TANK 2

XTAL 2

XTAL 1

FFQ

OSCIN

FFD

OSCOUT

φ3

VDD

φ4

φ1

φ2

GND 1

GND 2

VCC

φ1 TTL

φ2 TTL

φ3 TTL

φ4 TTL

130

Ω

150

Ω

+5V

50pF

VCO

'LS629

390pF

'00

CLEAR

CLOCK

1/2 '74

RECONSTRUCTED

CLOCK OUTPUT

MPX

INPUT

ONE SHOT

'121

GND

RINT

CEXT

REXT/CEXT

VCC

+5V

Ω

50pF

+5V

CLOCK

φ2

'74 (1/2)

CLOCK

RECONSTRUCTED

FREQUENCY OUTPUTS

φ3

'74 (1/2)

CLOCK

φ4

'74 (1/2)

NC = NO CONNECT

Figure 30. SVFC Demultiplexers

AD652BQ Datasheet(PDF) 21 Page - Analog Devices

AD652BQ Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Descarga

Enlace URL