AD652KP datasheet(24/29 Pages) AD

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AD652

Rev. C | Page 23 of 28

DELTA MODULATOR

The circuit of Figure 34 shows the AD652 configured as a delta

modulator. A reference voltage is applied to the input of the

integrator (Pin 7), which sets the steady state output frequency

at one-half of the AD652 full-scale frequency (1/4 of the clock

frequency). As a 0 V to 10 V input signal is applied to the

comparator (Pin 15), the output of the integrator attempts to

track this signal. For an input in an idling condition (dc), the

output frequency is one-half full scale. For positive-going

signals, the output frequency is between one-half full scale and

full scale; for negative-going signals, the output frequency is

between zero and one-half full scale. The output frequency

corresponds to the slope of the comparator input signal.

ONE

SHOT

AND

"D"

FLOP

QCK

1mA

20k

Ω

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

REFERENCE

+15V

360pF

0.0047

µF

–15V

CLOCK

VIN (0V TO 10V)

FOUT

+5V

0.01

µF

Ω

Figure 34. Delta Modulator

Since the output frequency corresponds to the slope of the input

signal, the delta modulator acts as a differentiator. A delta

modulator is thus a direct way of finding the derivative of a

signal. This is useful in systems where, for example, a signal

corresponding to velocity exists, and it is desired to determine

acceleration.

Figure 35 is a scope photo showing a 20 kHz, 0 V to 10 V sine

wave used as the input to the comparator and its ramp-wise

approximation at the integrator output. The clock frequency

used as 2 MHz and the integrating capacitor was 360 pF.

Figure 36 shows the same input signal and its ramp-wise

approximation, along with the output frequency corresponding

to the derivative of the input signal. In this case, the clock

frequency was 50 kHz.

The choice of an integrating capacitor is primarily dictated by

the input signal bandwidth. Figure 37 shows this relationship.

Note that as the value of CINT is lowered, the ramp size of the

integrator approximation becomes larger. This can be

compensated for by increasing the clock frequency. The effect of

the clock frequency on the ramp size is demonstrated in

Figure 35 and Figure 36.

Figure 35. Delta Modulator Input Signal and Ramp-Wise Approximation

Figure 36. Delta Modulator Input Signal Ramp-Wise Approximation and

Output Frequency

100

10k

100

10k

INPUT SIGNAL BANDWIDTH (Hz)

Figure 37. Maximum Integrating Cap Value vs. Input Signal Bandwidth

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