WM8768EDSSLASHR datasheet(19/38 Pages) WOLFSON

19 / 38 page

Production Data

WM8768

PD Rev 4.1 March 2005

DSP MODE B

In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8768 on the first BCLK

rising edge following a LRCLK rising edge. DAC channel 1 right and DAC channels 2/3/4 data follow

DAC channel 1 left data (Figure 17).

Figure 17 DSP Mode B Timing Diagram – DAC data input

In both DSP modes A and B, DACL1 is always sent first, followed immediately by DACR1 and the

data words for the other 8 channels. No BCLK edges are allowed between the data words. The word

order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right, DAC4 left, DAC4 right .

POWERDOWN MODES

The WM8768 has powerdown control bits allowing specific parts of the WM8768 to be powered off

when not being used. The four stereo DACs each have a separate powerdown control bit, DACD[2:0]

& DACD4, allowing individual stereo DACs to be powered off when not in use. Setting DACD will

power down everything except the reference VMID. This may be powered down by setting PDWN.

Setting PDWN will override all other powerdown control bits. It is recommended that the DACs are

powered down before setting PDWN.

LRCIN

BCKIN

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n-1

LSB

MSB

n-1

CHANNEL 1

RIGHT

CHANNEL 2

LEFT

n-1

CHANNEL 4

RIGHT

NO VALID DATA

WM8768EDS/R Datasheet(PDF) 19 Page - Wolfson Microelectronics plc