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AD6657ABBCZ Datasheet(PDF) 13 Page - Analog Devices

No. de pieza AD6657ABBCZ
Descripción Electrónicos  Quad IF Receiver
PDF  37 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD6657ABBCZ Datasheet(HTML) 13 Page - Analog Devices

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AD6657A
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
A5, A8, B5 to B8, D4 to
D9, E2 to E11
AVDD
Supply
Analog Power Supply. 1.8 V nominal.
A1, A4, A9, A12, B1, B2,
B4, B9, B11, B12, C2, C3,
C10, C11, D3, D10, E1,
E12, F1 to F12
AGND
Ground
Analog Ground.
H1 to H12
DRVDD
Supply
Digital Output Driver Supply. 1.8 V nominal.
G1 to G12
DRGND
Ground
Digital Output Driver Ground.
A7
CLK+
Input
ADC Clock Input—True.
A6
CLK−
Input
ADC Clock Input—Complement.
C12
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
D12
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
D11
VCMA
Output
Common-Mode Level Bias Output for Analog Input Channel A.
A11
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
A10
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
B10
VCMB
Output
Common-Mode Level Bias Output for Analog Input Channel B.
A2
VIN+C
Input
Differential Analog Input Pin (+) for Channel C.
A3
VIN−C
Input
Differential Analog Input Pin (−) for Channel C.
B3
VCMC
Output
Common-Mode Level Bias Output for Analog Input Channel C.
C1
VIN+D
Input
Differential Analog Input Pin (+) for Channel D.
D1
VIN−D
Input
Differential Analog Input Pin (−) for Channel D.
D2
VCMD
Output
Common-Mode Level Bias Output for Analog Input Channel D.
K7
D0+AB
Output
Channel A and Channel B LVDS Output Data 0—True.
J7
D0−AB
Output
Channel A and Channel B LVDS Output Data 0—Complement.
M7
D1+AB
Output
Channel A and Channel B LVDS Output Data 1—True.
L7
D1−AB
Output
Channel A and Channel B LVDS Output Data 1—Complement.
K8
D2+AB
Output
Channel A and Channel B LVDS Output Data 2—True.
J8
D2−AB
Output
Channel A and Channel B LVDS Output Data 2—Complement.
M8
D3+AB
Output
Channel A and Channel B LVDS Output Data 3—True.
L8
D3−AB
Output
Channel A and Channel B LVDS Output Data 3—Complement.
K9
D4+AB
Output
Channel A and Channel B LVDS Output Data 4—True.
J9
D4−AB
Output
Channel A and Channel B LVDS Output Data 4—Complement.
AGND
VIN+C
VIN–C
AGND
AVDD
CLK–
CLK+
AVDD
AGND
VIN–B
VIN+B
AGND
1
2
3
4
5
6
7
8
9
10
11
12
AGND
AGND
VCMC
AGND
AVDD
AVDD
AVDD
AVDD
AGND
VCMB
AGND
AGND
VIN+D
AGND
AGND
CSB
SDIO
SCLK
PDWN
SYNC
MODE
AGND
AGND
VIN+A
VIN–D
VCMD
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AGND
VCMA
VIN–A
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
DRVDD
D0–CD
D2–CD
D4–CD
D6–CD
D8–CD
D10–CD
D0–AB
D2–AB
D4–AB
D6–AB
D8–AB
D10–AB
D0+CD
K
D2+CD
D4+CD
D6+CD
D8+CD
D10+CD
D0+AB
D2+AB
D4+AB
D6+AB
D8+AB
D10+AB
D1–CD
D3–CD
D5–CD
D7–CD
D9–CD
DCO–CD
D1–AB
D3–AB
D5–AB
D7–AB
D9–AB
DCO–AB
D1+CD
A
B
C
D
E
F
G
H
J
L
M
D3+CD
D5+CD
D7+CD
D9+CD
DCO+CD
D1+AB
D3+AB
D5+AB
D7+AB
D9+AB
DCO+AB
Rev. A | Page 12 of 36



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