MFC2000 datasheet(61/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-31

External Chip Select Control Registers

Associated with each external chip select pin is a register to control automatic functions that will be executed

when a location within the chip select range is accessed. All bits default to 0 unless otherwise specified.

Several control functions are common between the various chip select register.

A chip select is enable when the enable bit is set to 1.

Wait states defines the number of wait states that are added to the associated bus cycle, in increments of

SIUCLK cycle. A bus cycle is 1 SIUCLK.

Size is the width of the external devices peripherals using the chip select. The allowable widths are 8 and 16 bits.

Size are coded : 0=byte, 1 = half-word. If the size of the data is larger than the size of the peripheral, the SIU will

automatically perform multiples accesses to complete the transaction. Default to 0.

Where applicable, Strobe Delay On = 1 delays the activation of RDn or WRn by 1 clk. Write Early Off deactivates

the WRn strobe by 1 clk earlier.

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

ROMCS

Control

(ROMCtrl)

01FF8803

(Not Used)

Rst. Value

xxh

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

ROMCS

Control

(ROMCtrl)

01FF8802

Read/Write

Strobe

Delay On

Mode[1]

(read only)

Mode[0]

(read only)

Subsequent

Wait

Wait[2]

Wait[1]

Wait[0]

Enable

Rst. Value

1??11111b

Read Value

1??11111b

Bit 7

Read/Write strobe Delay On

(default = 1)

Bits 6-5

Mode[1:0] ROM interface mode (read only). These 2 bits are read in

directly from 2 pins (the AE[2]/ROM_CFG[0] pin and the

AO[2]/ROM_CFG[1] pin during reset).

00: 8-bit Non Interleave

01: 16-bit Non interleave

10: 16-bit 2way interleave

11: 16-bit fast page mode

Bit 4

Subsequent access wait states in interleave mode (default = 1)

Bits 3-1

Wait states or initial access wait states in interleave mode (default = 7)

Bit 0

ROMCSn Enable.

(default = 1)

Note:

These controls are also applicable to the optional CS5n.

MFC2000 Datasheet(PDF) 61 Page - List of Unclassifed Manufacturers

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