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AD9445 Datasheet(PDF) 13 Page - Analog Devices |
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AD9445 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 41 page  AD9445 Rev. 0 | Page 12 of 40 Pin No. Mnemonic Description 83 D12− D12 Complement Output Bit. 84 D12+ D12 True Output Bit. 85 D13− D13 Complement Output Bit. 86 D13+ (MSB) D13 True Output Bit. 89 OR− Out-of-Range Complement Output Bit. 90 OR+ Out-of-Range True Output Bit. 100 RF ENABLE RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input frequencies <210 MHz for 125 MSPS speed grade and <230 MHz for the 105 MSPS speed grade. For applications with analog inputs >225 MHz for the 125 MSPS speed grade and >230 MHz for the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR performance. Power dissipation from AVDD2 increases by 150 mW to 200 mW. |
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