AD7656ABSTZ datasheet(24/29 Pages) AD

24 / 29 page

Data Sheet

AD7656A

Standby/Partial Power-Down Modes of Operation

(SER/PAR/SEL = 0 or SER/PAR/SEL = 1)

Each ADC pair can be individually placed into partial power-

down mode by bringing the CONVST x signal low before the

falling edge of BUSY. Bring the CONVST x signal high to power

up the ADC pair and place the track-and-hold amplifier into

track mode. After the power-up time from the partial power-

down has elapsed, the CONVST x signal typically receives a

rising edge to initiate a valid conversion. In partial power-down

mode, the reference buffers remain powered up. While an ADC

pair is in partial power-down mode, conversions can still occur

on the other ADCs.

The AD7656A has a power-down mode whereby the device can

be placed into a low power mode consuming 100 mW maximum.

The AD7656A is placed into standby mode by bringing the

logic input STBY low and can be powered up again for normal

operation by bringing STBY logic high. The output data buffers

are still operational when the AD7656A is in standby mode,

meaning the user can continue to access the conversion results

of the device. This standby feature can be used to reduce the

average power consumed by the AD7656A when operating at

lower throughput rates. The AD7656A can be placed into standby

at the end of each conversion when BUSY goes low and taken out

of standby again prior to the next conversion. The wake-up

time is when the AD7656A comes out of standby mode. The

wake-up time limits the maximum throughput rate at which the

AD7656A can operate when powering down between

conversions. See the Specifications section.

Rev. 0 | Page 23 of 28

AD7656ABSTZ Datasheet(PDF) 24 Page - Analog Devices