LTC1850CFW datasheet(15/28 Pages) LINER

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LTC1850/LTC1851

18501f

Table 2. Input Span Table

INPUT SPAN

UNI/BIP

PGA

REFCOMP = 4.096V

0 – REFCOMP/2

0 – 2.048V

0 – REFCOMP

0 – 4.096V

±REFCOMP/4

±1.024V

±REFCOMP/2

±2.048V

It should be noted that the bipolar input span of the

LTC1850/LTC1851 does not allow negative inputs with

respect to ground. The LTC1850/LTC1851 have a unique

differential sample-and-hold circuit that allows rail-to-rail

inputs. The ADC will always convert the difference of the

“+” and “–” inputs independent of the common mode

voltage. The common mode rejection holds up to high

frequencies. The only requirement is that both inputs can

not exceed the VDD power supply voltage or ground. When

a bipolar input span is selected the “+” input can swing

±full scale relative to the “–” input but neither input can

exceed VDD or go below ground.

Integral nonlinearity errors (INL) and differential nonlin-

earity errors (DNL) are independent of the common mode

voltage, however, the bipolar zero error (BZE) will vary.

The change in BZE is typically less than 0.1% of the

common mode voltage.

Some AC applications may have their performance lim-

ited by distortion. The ADC and many other circuits exhibit

higher distortion when signals approach the supply or

ground. THD will degrade as the inputs approach either

power supply rail. Distortion can be reduced by reducing

the signal amplitude and keeping the common mode

voltage at approximately midsupply.

Driving the Analog Inputs

The inputs of the LTC1850/LTC1851 are easy to drive.

Each of the analog inputs can be used as a single-ended

input relative to the input common pin (CH0-COM, CH1-

COM, etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4

and CH5, CH6 and CH7) for differential inputs. Regardless

of the MUX configuration, the “+” and “–” inputs are

sampled at the same instant. Any unwanted signal that is

common mode to both inputs will be reduced by the

common mode rejection of the sample-and-hold circuit.

The inputs draw only one small current spike while charg-

ing the sample-and-hold capacitors at the end of conver-

sion. During conversion, the analog inputs draw only a

small leakage current. If the source impedance of the

driving circuit is low, then the LTC1850/LTC1851 inputs

can be driven directly. As source impedance increases, so

will acquisition time. For minimum acquisition time with

high source impedance, a buffer amplifier should be used.

The only requirement is that the amplifier driving the

analog input(s) must settle after the small current spike

before the next conversion starts (settling time must be

150ns for full throughput rate).

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (<100

Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain of

+1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz should be less than 100

Ω.

The second requirement is that the closed-loop bandwidth

must be greater than 20MHz to ensure adequate small-

signal settling for full throughput rate. The following list is

a summary of the op amps that are suitable for driving the

LTC1850/LTC1851, more detailed information is available

in the Linear Technology Databooks, the LinearView

CD-ROM and on our web site at www.linear-tech.com.

®1360: 50MHz Voltage Feedback Amplifier.

±2.5V to

±15V supplies. 5mA supply current. Low distortion.

LT1363: 70MHz Voltage Feedback Amplifier.

±2.5V to

±15V supplies. 7.5mA supply current. Low distortion.

LT1364/LT1365: Dual and Quad 70MHz Voltage Feedback

Amplifiers.

±2.5V to ±15V supplies. 7.5mA supply current

per amplifier. Low distortion.

APPLICATIO S I FOR ATIO

LinearView is a trademark of Linear Technology Corporation.

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