ADV7174 datasheet(21/52 Pages) AD

No. de pieza	ADV7174

Descripción Electrónicos	Chip Scale PAL/NTSC Video Encoder with Advanced Power Management

PDF	52 Pages

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Fabricante Electrónico	AD [Analog Devices]

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21 / 52 page

ADV7174/ADV7179

Rev. A | Page 21 of 52

Mode 1: Master Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode, the ADV7174/ADV7179 can generate horizontal

SYNC and odd/even FIELD signals. A transition of the FIELD

input when HSYNC is low indicates a new frame, i.e., vertical

retrace. The BLANK signal is optional. When the BLANK input

is disabled, the ADV7174/ADV7179 automatically blanks all

normally blank lines as per CCIR-624. Pixel data is latched on

the rising clock edge following the timing signal transitions.

Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL).

Figure 26 illustrates the HSYNC, BLANK, and FIELD for an

odd or even field transition relative to the pixel data.

FIELD

PIXEL

DATA

PAL = 12

× CLOCK/2

NTSC = 16

× CLOCK/2

PAL = 132

× CLOCK/2

NTSC = 122

× CLOCK/2

HSYNC

BLANK

Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave

ADV7174 Datasheet(PDF) 21 Page - Analog Devices