LAN91C100FDREVB datasheet(47/68 Pages) SMSC

No. de pieza	LAN91C100FDREVB

Descripción Electrónicos	FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY

PDF	68 Pages

Scroll/Zoom	100%

Fabricante Electrónico	SMSC [SMSC Corporation]

Página de inicio	http://www.smsc.com

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47 / 68 page

SMSC DS – LAN91C100FD REV. B

Page 47

Rev. 05/31/2000

readback as both bits high. No other bits of the LAN91C100FD can be read or written until the EEPROM operation

completes and both bits are clear. This mechanism is also valid for reset initiated reloads.

Note: If no EEPROM is connected to the LAN91C100FD, for example for some embedded applications, the ENEEP pin

should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and Individual Address

assume their default values upon hardware reset and the CPU is responsible for programming them for their final value.

FIGURE 12 - 64 X 16 SERIAL EEPROM MAP

CONFIGURATION REG.

BASE REG.

CONFIGURATION REG.

BASE REG.

CONFIGURATION REG.

BASE REG.

CONFIGURATION REG.

BASE REG.

CONFIGURATION REG.

BASE REG.

CONFIGURATION REG.

BASE REG.

CONFIGURATION REG.

BASE REG.

IA0-1

IA2-3

IA4-5

IOS2-0

WORD ADDRESS

000

10h

11h

14h

15h

18h

19h

20h

21h

22h

001

010

011

100

101

110

XXX

16 BITS

LAN91C100FDREVB Datasheet(PDF) 47 Page - SMSC Corporation

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