WM8978GEFLSLASHV datasheet(66/78 Pages) WOLFSON

66 / 78 page

WM8978

Product Preview

PP Rev 1.7 January 2005

BIASEN

The analogue amplifiers will not operate unless BIASEN is enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 1

BIASEN

Analogue amplifier bias control

Table 57 Analogue Bias Control

ESTIMATED SUPPLY CURRENTS

When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from

DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an

additional 700 microamps will be drawn from DCVDD.

Table 58 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit.

AVDD CURRENT (MILLIAMPS)

BUFDCOPEN

0.1

OUT4MIXEN

0.2

OUT3MIXEN

0.2

PLLEN

1.4 (with clocks applied)

MICBEN

0.5

BIASEN

0.3

BUFIOEN

0.1

VMIDSEL

10K=>0.3, less than 0.1 for 100k/500k

ROUT1EN

0.4

LOUT1EN

0.4

BOOSTENR

0.2

BOOSTENL

0.2

INPPGAENR

0.2

INPPGAENL

0.2

ADCENR

x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9

ADCENL

x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9

OUT4EN

0.2

OUT3EN

0.2

LOUT2EN

1mA from SPKVDD + 0.2mA from AVDD in 5V mode

ROUT2EN

1mA from SPKVDD + 0.2mA from AVDD in 5V mode

RMIXEN

0.2

LMIXEN

0.2

DACENR

x64 (DACOSR=0)=>1.8, x128(DACOSR=1)=>1.9

DACENL

x64 (DACOSR=0)=>1.8, x128(DACOSR=1)=>1.9

Table 58 AVDD Supply Current

WM8978GEFL/V Datasheet(PDF) 66 Page - Wolfson Microelectronics plc

WM8978GEFL/V Datasheet(HTML) 66 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Descarga

Enlace URL