WM8972LEFLSLASHR datasheet(31/49 Pages) WOLFSON

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Preliminary Technical Data

WM8972L

PTD Rev 2.2 June 2004

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised in

Table 24. MS selects audio interface operation in master or slave mode. In Master mode BCLK,

ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the sample

rate control bits SR[4:0] and USB. In Slave mode BCLK, ADCLRC and DACLRC are inputs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

BCLKINV

BCLK invert bit (for master & slave

modes)

0 = BCLK not inverted

1 = BCLK inverted

Master / Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

right, left & i2s modes – LRCLK polarity

1 = invert LRCLK polarity

0 = normal LRCLK polarity

LRP

DSP Mode – mode A/B select

1 = MSB is available on 1st BCLK rising

edge after LRC rising edge (mode B)

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

3:2

WL[1:0]

Audio Data Word Length

11 = 32 bits (see Note)

10 = 24 bits

01 = 20 bits

00 = 16 bits

R7 (07h)

Digital Audio

Interface

Format

1:0

FORMAT[1:0]

Audio Data Format Select

11 = DSP Mode

10 = I

2S Format

01 = Left justified

00 = Right justified

Table 24 Audio Data Format Control

Note: Right Justified mode does not support 32-bit data.

AUDIO INTERFACE OUTPUT TRISTATE

DACLRC and BCLK to inputs. In Slave mode (MASTER=0) ADCLRC, DACLRC and BCLK are by

default configured as inputs and only ADCDAT will be tri-stated, (see Table 25).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24(18h)

Additional

Control (2)

TRI

Tristates ADCDAT and switches ADCLRC,

DACLRC and BCLK to inputs.

0 = ADCDAT is an output, ADCLRC, DACLRC

and BCLK are inputs (slave mode) or outputs

(master mode)

1 = ADCDATE is tristated, ADCLRC, DACLRC

and BCLK are inputs

Table 25 Tri-stating the Audio Interface

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